This application claims the benefit of Korean Patent Application No. 2000-04643, filed Jan. 31, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to integrated circuit devices and, more particularly, to integrated circuit memory devices having multiple input/output buses.
Integrated circuit memory devices, particularly dynamic access memories (DRAMs), are widely used in electronic systems for storing large volumes of digital information. As electronic systems operate at more rapid processing speeds, however, the access times for reading data from or writing data to a DRAM may become an important parameter when designing a high-performance electronic system.
Various techniques for improving the access time of a DRAM have been developed. According to one method known as xe2x80x9cnibble mode,xe2x80x9d access time delay may be reduced by constructing a DRAM so that four sequential bits may be accessed rapidly and sequentially. According to another method known as xe2x80x9cburst mode,xe2x80x9d data bits belonging to a row (e.g., a word line) may be sequentially accessed after a first data bit is accessed. This method may also be referred to as xe2x80x9cpull page mode.xe2x80x9d After inputting an initial address in burst mode operation, sequential addresses are internally and sequentially generated without inputting new address information to the DRAM. According to the aforementioned methods, the access time of a DRAM may be improved by reducing and/or eliminating the delay time that is needed to fetch an address associated with the respective access of sequential bits.
FIG. 1 is a diagram that illustrates a relationship between a memory cell array and pairs of input/output lines in a conventional dynamic random access memory device. A memory cell array 1 includes a plurality of word lines WLi (i=0xe2x88x92m), a plurality of bit line pairs BLj and BLjB (=0xe2x88x92n), and a plurality of memory cells 10. A plurality of column select switches 20 are connected between sense amplifiers SA, which are each connected to a bit line pair, and input/output line pairs I/O0, I/O0B, I/O1, I/O1B, I/O2, I/O2B, I/O3, and I/O3B, as shown. The input/output line pairs I/O0, I/O0B, I/O1, and I/O1B are arranged on one side of the memory cell array 1 (i.e., the left side in FIG. 1), and the input/output line pairs I/O2, I/O2B, I/O3, and I/O3B are arranged on another side of the memory cell array 1 (i.e., the right side in FIG. 1). The input/output line pairs form input/output buses, which may be shared by adjacent memory cell arrays (not shown). That is, the input/output line pairs I/O0, I/O0B, I/O1, and I/O1B at the left side of the memory cell array 1 form a left input/output bus, and the input/output line pairs I/O2, I/O2B, I/O3, and I/O3B at the right side of the memory cell array 1 form a right input/output bus. The input/output lines comprising the respective data buses transfer 2-bits of data.
Column select lines CSL0 through CSLk are respectively connected to the column select switches 20 for accessing two bit line pairs via the left input bus and two bit line pairs via the right input bus. Therefore, when a column select line is chosen, 2-bits of data may be transferred through the left and right input/output buses, respectively (i.e., 4-bits of data may be input/output). Corresponding drivers 30 are connected to one end of each input/output line pair on the left side of the memory cell array 1. Each driver 30 may supply data to be written to the memory cell array 1 through associated input/output line pairs in response to a signal CA11B. Similarly, corresponding drivers 30 are connected to one end of each input/output line pair on the right side of the memory cell array 1. Each driver 30 may supply data to be written to the memory cell array 1 through associated input/output line pairs in response to a signal CA11.
In a DRAM having the foregoing input/output structure, the memory cell array may be accessed through the right and left input/output buses simultaneously, or, alternatively, through one of the input/output buses through control of the signals CA11 and CA11B. For example, when the signal CA11B is activated and the signal CA11 is deactivated, the drivers 30 connected to the left input/output bus are selected, while the drivers 30 connected to the right input/output bus are unselected. Conversely, when the signals CA11 and CA11B are activated simultaneously, the drivers 30 connected to the left and right input/output buses are selected at the same time.
The DRAM shown in FIG. 1 may be operated in a pull page mode as discussed hereinabove. In the pull page mode, all memory cells connected to a selected word line are sequentially accessed. A write operation of the DRAM in pull page mode may be carried out in multiple ways: In one approach, after data are written to memory cells coupled to a selected word line through an input/output bus at one side of the memory cell array 1, data are then written to memory cells coupled to a selected word line through an input/output bus at the other side of the memory cell array 1. In another approach, data are written simultaneously to all memory cells coupled to a selected word line through the input/output buses at both sides of the memory cell array 1. Unfortunately, when performing a pull page mode write operation according to the first approach described above, a problem may arise as follows.
To carry out a write operation through the left input/output bus, the signal CA11B is activated and the signal CA11 is deactivated. As a result, the drivers 30 connected to the left input/output bus are selected and the drivers 30 connected to the right input/output bus are unselected. The selected drivers 30 supply data to be written to the memory cell array 1 through the left input/output bus, which is connected to selected memory cells through column select switches 20 and sense amplifiers SA associated with a first column select line CSL0. Data are then sequentially written to the remaining memory cells by sequentially activating remaining column select lines in the same manner as described above.
When the signal CA11B is deactivated and the signal CA11 is activated, the drivers 30 connected to the right input/output bus are selected and the drivers 30 connected to the left input/output bus are unselected. The selected drivers 30 supply data to be written to the memory cell array 1 through the right input/output bus. At this time, the left input/output bus connected to the unselected drivers 30 is maintained in a floating state. Data on the right input/output bus is written to selected memory cells through column select switches 20 and sense amplifiers SA associated with the first column select line CSL0. When the first column select line CSL0 is selected to perform a write operation through the right input/output bus, charges on the left input/output bus, which remain after the write operation has been performed through the left input/output bus, are written to the memory cells identified by the dotted line through column select switches 20 and sense amplifiers SA arranged on the left side of the memory cell array 1. This unintended corruption of data stored in the memory cell array 1 may be referred to as a xe2x80x9cbit line disturbance phenomenon.xe2x80x9d As may be seen from FIG. 1, when a column select line is selected, the left input/output bus is connected to corresponding memory cells through associated column select switches 20 and sense amplifiers SA, and the right input/output bus is simultaneously connected to corresponding memory cells through associated column select switches 20 and sense amplifiers SA. As a result, data stored in the memory cell array may be corrupted when performing a write operation through one of the input/output buses following the completion of a write operation on the other one of the input/output buses.
Embodiments of the present invention include integrated circuit memory devices and methods of writing data thereto in which first and second input/output buses are coupled to a memory cell array. A precharge controller circuit generates a precharge control signal in response to completion of a write operation on the first input/output bus. A precharge circuit drives the first and second input/output buses to a predetermined voltage level in response to the precharge control signal.
Multiple switches may be used to couple the first and second input/output buses to the memory cell array and these switches may also be coupled to a column select line. The switches may be responsive to a column select signal carried on the column select line such that one or more memory cells are coupled to the first input/output bus and one or more memory cells are coupled to the second input/output bus simultaneously. Because both of the input/output buses are coupled to the memory cell array in response to the column select signal, the memory cell array may be susceptible to bit line disturbance in which charges remaining on one input/output bus from a previous write operation corrupt memory cells during a write operation on a second input/output bus. By driving the first and second input/output buses to a predetermined voltage level after completing a write operation on one of the two input/output buses, bit line disturbance may be prevented.
In particular embodiments, the first and second input/output buses are electrically coupled to first and second driver circuits, respectively, which are responsive to a driver control signal. The first and second driver circuits may supply data to be written into the memory cell array through the respective first and second input/output buses. A column select circuit that comprises, for example, a counter, may be used to generate the column select signal and the driver signal.
In further embodiments, the precharge controller circuit comprises a flag signal generator that generates a flag signal in response to completion of a write operation on the first input/output bus, and a precharge signal generator that generates the precharge control signal in response to the flag signal. The precharge circuit may comprise multiple precharge transistors.
Thus, the present invention may provide improved data integrity by preventing bit line disturbance in a memory cell array by driving first and second input/output buses to a predetermined voltage level between respective write operations on the first and second input/output buses.